FPGA implementation of compact S-Box for AES algorithm using composite field arithmetic

Abstract

This paper present method for constructions of the S-Box for Advanced Encryption Standard (AES) algorithm using composite field arithmetic in GF(((22)2)2). It is advantageous to implement the composite field arithmetic (CFA) on Field Programmable Gate Array for AES algorithm. Moreover, architectural implementation of S-Box using CFA reduces the hardware in terms of gates count as compared with that classical Look Up Table based S-Box for AES algorithm. The composite fields are constructed by decomposition methodology. However, an isomorphic mapping function to map the GF (28) representation to its composite field in GF (((22)2)2) and eight such mappings exist for each construction. The proposed CFA based S-Box implementation on hardware provides less area by 50% and low power consumption compared to the classical S-Box.