A High-Resolution Digital Phase Interpolator Based CDR with a Half-Rate Hybrid Phase Detector

Abstract

In this paper, we propose a low power, high-resolution digitally controlled phase interpolator based clock and data recovery (CDR) architecture for high-speed serial links. This architecture incorporates a half-rate hybrid phase detector (HyPD) consisting of a linear phase detector with a 2-tap decision feedback equalizer (DFE), a 1-bit comparator, and an 8-bit digitally controlled phase interpolator. HyPD results in better power performance over the bang-bang phase detector. DFE used in HyPD combats the effect of inter-symbol-interference (ISI) and improves the sampling margins. The phase interpolator provides an unlimited phase capture with a resolution of 1.41° per LSB for varying phase of the input clock. The differential and integral nonlinearities of the DAC based phase interpolator are within ±0.28 LSB and ±0.3 LSB respectively, which lead to low jitter in the recovered clock. We have designed a 5 Gb/s CDR in a 0.18-µm standard CMOS technology. It draws 23.4 mW of power from a 1.8-V supply.