A Highly Reliable Strong Physical Unclonable Function Design Based on FPGA

Abstract

Physical unclonable function (PUF) generates unique secret keys from unavoidable IC manufacturing variations, which can eliminate high computation expense and additional key storage. The inherent flexibility and lower time-to-market have made field programmable gate array (FPGA) the platform of choice for faster implementation. However, logic elements on FPGA are predefined while some types of PUFs need strictly mirrored symmetric routing. This paper presents a robust and FPGA friendly PUF based on oscillator collapse (OC-PUF) with million number of challenge-response pairs (CRPs). Mirrored routes are obtained with a novel delay cell design and a signal path configuration technique. In the meanwhile, the response bias issues on FPGA is effectively resolved. Measured on Altera DE2-115, the average interchip hamming distance (inter-chip HD) of the proposed OC-PUF is 46.7%. After applying dynamic threshold with a value 255, intra-chip hamming distance (intra-chip HD) dropped to 5.46E-06 at nominal conditions.