A highly reliable 256-kb MNOS EEPROM: Memory cell design technology

Abstract

Memory cell design technology for highly reliable 256-kb MNOS EEPROM has been established. It realizes 10-year data retention and 105 erase/write cycle endurance. An MNOS memory device is composed of a 24-nm Si3N4 layer and a 1.6-nm tunnel SiO2 layer. The programming voltage is 13 ± 1 V supplied from internal high-voltage generator. A wide operating margin has been obtained in which the lower limit ensures the retention of the written state and the upper limit ensures the endurance of the erased state. Using 1.3-μm CMOS fabrication technology, the data line pitch is 6.7 μm and the word line pitch is 7.8 μm. As a result, the MNOS memory cell size is designed to be 52.26 μm2, and the chip size is the smallest one such as 33.16 mm2 in 256-kb EEPROMs.