Abstract
For a complementary metal-oxide-semiconductor image sensor with highly linear, low noise and high frame rate, the nonlinear correction and frame rate improvement techniques are becoming very important. The in-pixel source follower transistor and the integration capacitor on the floating diffusion node cause linearity degradation. In order to address this problem, this paper proposes an adaptive nonlinear ramp generator circuit based on dummy pixels used in single-slope analog-to-digital converter topology for a complementary metal-oxide-semiconductor (CMOS) image sensor. In the proposed approach, the traditional linear ramp generator circuit is replaced with the new proposed adaptive nonlinear ramp generator circuit that can mitigate the nonlinearity of the pixel unit circuit, especially the gain nonlinearity of the source follower transistor and the integration capacitor nonlinearity of the floating diffusion node. Moreover, in order to enhance the frame rate and address the issue of high column fixed pattern noise, a new readout scheme of fully differential pipeline sampling quantization with a double auto-zeroing technique is proposed. Compared with the conventional readout structure without a fully differential pipeline sampling quantization technique and double auto-zeroing technique, the proposed readout scheme cannot only enhance the frame rate but can also improve the consistency of the offset and delay information of different column comparators and significantly reduce the column fixed pattern noise. The proposed techniques are simulated and verified with a prototype chip fabricated using typical 180 nm CMOS process technology. The obtained measurement results demonstrate that the overall nonlinearity of the CMOS image sensor is reduced from 1.03% to 0.047%, the efficiency of the comparator is improved from 85.3% to 100%, and the column fixed pattern noise is reduced from 0.43% to 0.019%.
Highlights
Linear complementary metal-oxide-semiconductor (CMOS) image sensors (CISs) have a wide range of applications in time-of-flight (ToF) ranging, medical imaging, space remote sensing imaging and scientific imaging [1,2,3,4,5,6]
In order to address the above-mentioned problems, this paper proposes an adaptive nonlinear ramp generator circuit design and a readout circuit with fully differential pipeline sampling quantization based on the double AZ technique
The CMOS image sensor (CIS) proposed in this paper consists of a typical 5T pixel [6] array, an adaptive nonlinear ramp generator, a readout circuit with fully differential pipeline sampling quantization based on the double AZ technique, row/column decoder and driver, timing sequence controller, phase-locked loop (PLL), charge pump, temperature sensor, and high-speed, high-precision, low-power LVDS serial data transfer circuit
Summary
Linear complementary metal-oxide-semiconductor (CMOS) image sensors (CISs) have a wide range of applications in time-of-flight (ToF) ranging, medical imaging, space remote sensing imaging and scientific imaging [1,2,3,4,5,6]. The fourth type is utilizing the off-chip high-precision ADC and digital-to-analog converter (DAC) to calibrate the nonlinearity of the CMOS image sensor system [1,2,3,15]. The advantages of this correction method are high linearity and high precision. In the literature [6], a classic CIS composed of a programmable gain amplifier (PGA) and an SS-ADC has been proposed for the column-level readout circuit. In order to address the above-mentioned problems, this paper proposes an adaptive nonlinear ramp generator circuit design and a readout circuit with fully differential pipeline sampling quantization based on the double AZ technique.
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