A highly efficient dynamic router for application-oriented network on chip

Abstract

With the number of processor cores increasing in chip multiprocessors, the network on chip becomes a reliable structure with its perfect parallel communication performance. The traditional static router suffers a bad performance because of low buffer utilization for application-oriented network on chip. In this paper, a dynamic router which can take into account the unbalanced traffic for application-oriented network on chip is proposed. The router combines the inter-port and intra-port buffer allocation mechanism, which makes efficient use of buffer resources and avoids the head of line blocking. Furthermore, the proposed router can solve the problem of unbalanced load effectively between different ports on the same router. Simulation results show that the on-chip routers balance traffic between ports and increase the buffer utilization by 21.8%, thus optimizing delay and throughput performance for application-oriented network on chip.