A highly efficient and secure hardware implementation of the advanced encryption standard

Abstract

A highly efficient and power analysis attack robust architecture for hardware implementation of the advanced encryption standard algorithm (AES) is presented. By choosing a correct topology the required resources for the FPGA implementation of the AES algorithm have been reduced. In addition, by using an innovative scheme which combines a randomized SBox with a modified Boolean masking technique, the correlation between Hamming distance of sensitive data and power consumption of the algorithm on target platform is removed. The robustness of the proposed outer masking which is a modified version of the existing first-order Boolean masking scheme is evaluated by the Welch's t-test statistical analysis and also experimental results while the efficiency of the internal randomization technique inside the SBox module is based on the randomization in the underlying composite field GF(24)2. The proposed implementation outperforms other proposals presented in the open literature as the results from the Place and Route report indicate that area occupied by the unprotected architecture is 746 slices with a maximum clock frequency of 318.4 MHz on Virtex-5 FPGA while the protected implementation consumes 966 slices with a maximum frequency of 310.4 MHz.