A high-gain low-noise distributed amplifier with low DC power in 0.18-µm CMOS for vital sign detection radar

Abstract

A new topology of distributed amplifier (DA) is developed in 0.18-µm CMOS. The topology uses the combination of the DA with taper-sized transistors and the cascaded singlestage distributed amplifier (CSSDA). This proposed DA takes considerations of gain-band width (GBW) product, output power, noise figure (NF), dc power consumption, and compact size. By using DA with taper-sized transistors, this DA reduces dc power consumption while maintaining the RF performance. This DA achieves 25-dB gain and 34 GHz 3-dB bandwidth with total dc power of 176 mW. The maximum OP 1dB is 7.2 dBm and the NF is between 6.5 and 8 dB at frequency lower than 25 GHz with the compact size of 0.86 mm2. This circuit exhibits the best figure of merit (FOM) in 0.18-µm CMOS and comparable performance with the DAs in advanced process.