Abstract
A 14-to-9l GHz distributed amplifier (DA) composed of a conventional distributed amplifier (CDA) and a cascaded single-stage distributed amplifier (CSSDA) in 65-nm CMOS is presented. To broaden the gain bandwidth and enhance the high-frequency small signal gain, the DA adopts the technique of multi-drive inter-stack coupling. According to the measured results, the proposed DA demonstrates a small signal gain of 30 dB, a 3-dB bandwidth of 77 GHz, and a gain-bandwidth product of 2435 GHz with total dc power of 254mW. The maximum OP 1dB is 7.4 dBm between 40 and 67 GHz, and the noise Figure is between 5.9 and 7.2 dB from 10 to 42 GHz. The chip size of the DA is 0.62 mm2. To authors’ knowledge, this circuit performs highest gainbandwidth (GBW) product in the CMOS process with DA topology.
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