Abstract
A high-speed moving average integrator in silicon photonics is demonstrated. The integrator is monolithically fabricated with an optical receiver front-end operating at 1550 nm. The design consists of an optical splitter, an optical low-loss delay line to implement a 400 ps delay between the two received bit streams, two SiGe photodiodes, and a 200 fF capacitor. The proposed moving average structure can perform four-bit integration at 10 Gbps. The resulting signal at the output of the integrator is the moving average of the received bit streams. The moving average integrator is validated through measurements and simulations at 2.5 and 5 Gbps. The proposed structure facilitates the development of next generation cost-effective and energy-efficient optical transceivers by exploiting optical time delay and moving average operation in silicon photonics. This mitigates the need for multiple clock phase generation and trans-impedance amplification on the electronic chip.
Highlights
S ILICON Photonics (SiP) plays a key role in addressing the ever-increasing demand for optical transceivers with high bandwidth and low power consumption for future data centers
The power consumption of a highgain transimpedance amplifier (TIA) and the clock-phase generation circuit in 40 nm CMOS node can be beyond 42 % of the power budget of the CMOS receiver front-end [3]
The delay line consists of a low-loss rib silicon waveguide with a width of 3 μm and a core thickness of 220 nm surrounded by a 90 nm thick slab, as depicted in the inset of Fig. 1(b)
Summary
S ILICON Photonics (SiP) plays a key role in addressing the ever-increasing demand for optical transceivers with high bandwidth and low power consumption for future data centers. A moving average integrator is monolithically combined with an optical receiver structure in silicon photonics With this approach, is the charge sharing issue resolved, which leads to enhanced sensitivity, and, there is no need for generating a short duration reset pulse. Is the charge sharing issue resolved, which leads to enhanced sensitivity, and, there is no need for generating a short duration reset pulse This structure enables a photonic-electronic co-design approach for data communications that does not need a complicated clock-phase generation circuitry and a TIA on the CMOS chip (TIA-less) and, significantly improves the power consumption of the receiver
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