A Survey of Optical and Electronic Delay Lines with a Case Study on Using Optical Delay Lines in 65 nm CMOS Optical Receivers

Abstract

This paper presents a survey of electronic delay lines and recent advances in silicon photonics-based optical delay lines targeting data and clock synchronization in the optical receiver. Important considerations such as delay range, delay resolution, tunability, and power consumption are discussed. Measurements of two optical receivers developed in CMOS 65 nm utilizing silicon photonic based delay lines are presented demonstrating the benefits of optical delays. Superior energy efficiency of 156 fJ/bit is achieved at 17 Gb/s.