Abstract
A split-gate deep-trench MOSFET (DT-MOS) with its split gate self-biased to an integrated low voltage supply is proposed. Due to the split gate being biased to an approximately constant voltage, this structure has a smaller amount of gate-to-drain charge Q <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gd</sub> without increase in the specific on-resistance R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> , compared with the conventional DT-MOS. Numerical simulation results show that the figure of merit (FOM = Q <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gd</sub> ·R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> ) is largely reduced, compared with that of the conventional DT-MOS.
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