A high-speed and low-offset dynamic latch comparator.

Labonnah Farzana Rahman,Mohammad Marufuzzaman,Mohammad Anisur Rahman,Mamun Bin Ibne Reaz,Chia Chieu Yin

doi:10.1155/2014/258068

Labonnah Farzana Rahman, Mohammad Marufuzzaman + Show 3 more

Open Access

https://doi.org/10.1155/2014/258068

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Abstract

Circuit intricacy, speed, low-offset voltage, and resolution are essential factors for high-speed applications like analog-to-digital converters (ADCs). The comparator circuit with preamplifier increases the power dissipation, as it requires higher amount of currents than the latch circuitry. In this research, a novel topology of dynamic latch comparator is illustrated, which is able to provide high speed, low offset, and high resolution. Moreover, the circuit is able to reduce the power dissipation as the topology is based on latch circuitry. The cross-coupled circuit mechanism with the regenerative latch is employed for enhancing the dynamic latch comparator performance. In addition, input-tracking phase is used to reduce the offset voltage. The Monte-Carlo simulation results for the designed comparator in 0.18 μm CMOS process show that the equivalent input-referred offset voltage is 720 μV with 3.44 mV standard deviation. The simulated result shows that the designed comparator has 8-bit resolution and dissipates 158.5 μW of power under 1.8 V supply while operating with a clock frequency of 50 MHz. In addition, the proposed dynamic latch comparator has a layout size of 148.80 μm × 59.70 μm.

Highlights

Analog-to-digital converters (ADC) have become a significant element driving the semiconductor industry over the past few years
The CADENCE Virtuoso in a 0.18 μm CMOS process parameter is utilized in this design
A novel high-speed, low power, and low-offset dynamic latchtype comparator method is presented in this research work

Summary

Introduction

Analog-to-digital converters (ADC) have become a significant element driving the semiconductor industry over the past few years. Some features of ADCs like small size processes, low power indulgences, and a reduced propagation delay make them more acceptable to the semiconductor industry. Analog circuit design happens to be more complex to carry out the necessity of reliability, where supply voltages need to be decreased according to the small dimensions of the transistors [2]. All these concerns apply to the most usable representative of the ADCs: the comparator

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