A High Precision Output Impedance Calibration Technique for SST Transmitter

Abstract

This paper presents a high precision output impedance calibration technique for source-series terminated (SST) transmitter. Unlike the conventional impedance calibration technique using a digital method, the proposed impedance calibration employs the analog method to implement the impedance calibration. Therefore, there is no trade-off between area overhead and precision of calibration. The proposed analog impedance calibration circuit has three analog impedance control loops, namely, pull-up loop, pull-down loop and shunt-loop. Each loop is composed of a high gain amplifier and a slice-based unit. To reduce the hardware, the shunt loop utilized a slice unit replication design to achieve the shunt-slice calibration. These loops send output voltage to the SST transmitter when they reached stability. Fabricated in 55[Formula: see text]nm CMOS technology, the power consumption of the calibration circuit is 1.35[Formula: see text]mW and the total area is 61[Formula: see text][Formula: see text]m*83.1[Formula: see text][Formula: see text]m, which consumes 6.3% of the total power consumed by the transmitter and occupies 25% of the total area occupied by the complete transmitter. The post-layout simulation result shows that the maximum impedance calibration error of the three loops is less than 0.02%.