A high performance synthesisable unsymmetrical reconfigurable fabric for heterogeneous finite state machines

Abstract

The use of synthesizable reconfigurable cores in system on chip (SoC) designs is increasingly becoming a trend. Such domain-special cores are being used for their flexibility, powerful function and low power consumption. A reconfigurable finite state machine (FSM) is constantly required for the purpose of control in any reconfigurable SoC. This paper presents a novel unbalanced unsymmetrical reconfigurable architecture for generic FSM; compared with commercial FPGA devices, the new architecture results in area reduction of 43% and power consumption decrease of 82%.