Abstract
This proposed paper presents the design and simulation results of a high performance CMOS operational amplifier in 90nm digital CMOS process. The operational amplifier (op-amp) circuit operates with high DC gain, high unity gain bandwidth, higher values of slew rate and draws less power. The transistor size in the op-amp circuit is designed, validated and operated at V DD =1.5V. A current buffer circuit is included in the intermediate stages of the circuit. A tradeoff between low power consumption and high speed of operation is considered in this work. The proposed high performance op-amp circuit is simulated using Tanner Spice simulator in 90nm technology. The op-amp provides a DC gain of 88dB and a unity gain bandwidth of 1.45GHz at 0.5pF. The slew rate of the amplifier circuit is calculated as174.2 V/µS, CMRR is 92dB and area is 0.042mm2. The power dissipation of the designed op-amp circuit is measured to be 224.8µW.
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