A high performance architecture design of PLC dedicated processor

Abstract

In order to improve the speed of executing PLC instructions, the high performance PLC processor is researched. The proposed high performance PLC dedicated processor consists of the general processor and the PLC application specific instruction set processor (ASIP), and regards the PLC ASIP as the core. In the PLC ASIP, four kinds of instruction formats and five kinds of instruction sets are designed. The architecture is designed to accelerate the instructions execution. The PLC ASIP can improve the speed of executing bool instructions, load and store instructions and function block instructions, which occupy 70.4% frequency of PLC instructions. The general processor is used for compiling the PLC concurrent program, controlling the peripheral equipments and executing arithmetic instructions. The general processor and the PLC ASIP can execute concurrently, when executing instructions in the two processors are independent with each other. The proposed design helps to improve real-time performance, comparing to the traditional sequential execution of PLC program. To validate the advance of the proposed design, three ladder programs are compiled to the instruction set of diversified processor. Compared the number of compiled instructions of diversified processor, the number of compiled instructions of the PLC dedicated processor are smallest.