A High Layer Scalability TSV-Based 3D-SRAM With Semi-Master-Slave Structure and Self-Timed Differential-TSV for High-Performance Universal-Memory-Capacity-Platforms

Abstract

TSV-based 3D die-stacking technology enables the reuse of pre-designed, pre-tested logic dies stacked with multiple memory layers ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">STACK</sub> ) in various configurations to form a universal-memory-capacity platform (UMCP). However, conventional 3D memories suffer speed, power and yield overheads due to the large parasitic load of TSV and cross-layer PVT variations when implemented in large <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">STACK</sub> with wide IO, especially using via-last TSVs. This work proposes a semi-master-slave (SMS) memory structure with self-timed differential-TSV signal transfer (STDT) scheme to improve the speed, power, and yield of 3D memory devices, while providing high scalability in <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">STACK</sub> for 3D-UMCP. The SMS scheme achieves the following: 1) a constant-load logic-SRAM interface across various <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">STACK</sub> ; 2) high tolerance for variations in cross-layer PVT, and 3) at-speed pre-bonding KGD sorting. The STDT scheme employs a TSV-load tracking scheme to achieve small TSV voltage swing for suppressing power and speed overheads of cross-layer TSV signal communication resulting from large TSV parasitic loads, particularly in UMCP designs with scalable <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">STACK</sub> and wide-IO. To verify the viability of the proposed structure and scheme, we developed a 2-layer 32 kb 3D-SRAM testchip with layer-scalable test-modes using a via-last TSV process with die-to-die bonding. This testchip confirmed the functionality and demonstrated superior scalability in <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">STACK</sub> with small speed overheads.