Challenges of CMP technology for 3D memories

Abstract

This paper presents an overview of technical trends and challenges of CMP technology for 3D memories. Large-capacity nonvolatile memories have been expanding the market for external storage devices for mobile products, and are utilized in all areas of people's daily lives. Toshiba's memory business has consistently realized innovations in various leading-edge technologies as the inventor of flash memory. Although the challenges over the physical scaling limit will become steep, we are aiming to overcome such issues by making use of our long-accumulated experience and record of innovations [1]. Ultrahigh-density memory technologies to realize a three-dimensional (3D) memory cell array have been attracting considerable interest as a solution to deal with the continuous increase in bit density and reduction of bit cost expected in the future. Applying its proprietary technologies, Toshiba has developed the world's first bit-cost scalable (BiCS) flash memory technology to achieve a 3D memory cell array with an extremely low fabrication cost [2]. A feature of BiCS technology is that a whole stack of electrode plates is punched through and plugged by another material to form a three-dimensional memory cell array as shown in Fig. 1. This fabrication process is expected to achieve a continuous reduction in bit-cost, since the number of processes will not significantly rise against increases in the number of layers for future ultrahigh-density memories [3] [4]. The planarization method by chemical mechanical polishing (CMP) has become the standard technology for semiconductor device manufacturing. Important challenges of the CMP technology for the 3D memory manufacturing are higher planarity and higher productivity. BiCS requires higher planarity of interlayer dielectric film (ILD) in staircase and peripheral region. The maximum step height is much larger than that of 2D flash memory devices due to formation of the stacked films. Therefore, it becomes very difficult to obtain higher planarity. Furthermore, BiCS requires large number of CMP process steps because of formation of plugs and wirings in staircase region compared with 2D flash memory devices. Throughput enhancement of CMP process is necessary for higher productivity. Innovative CMP technologies to realize higher planarity and higher productivity are expected for next generation 3D memory devices.