A High-Density Memory Design Based on Self-Aligned Tunneling Window for Large-Capacity Memory Application

Chen Wang ,Xin Chao,Hao Zhu,Xiuli Zhao,Hao Líu ,Qingqing Sun

doi:10.3390/electronics10161954

Chen Wang , Xin Chao + Show 4 more

Open Access

https://doi.org/10.3390/electronics10161954

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Abstract

Despite the continuous downscaling of complementary metal–oxide–semiconductor (CMOS) devices, various scenarios of technology have also been proposed toward the shrinking of semiconductor memory. In this paper, a high-density memory (HDM) has been proposed on the basis of band-to-band tunneling (BTBT) for low-power, high density, and high-speed memory applications. The geometric structure and electrical properties have been demonstrated by using TCAD tools. Typical memory operations including read, program, and erase have been designed and performed. High operation speed, lower power consumption, as well as good reliability characteristics have been achieved by simulation, which indicates that the HDM may have potential application value as a novel semiconductor memory device.

Highlights

Static random-access memory (SRAM) has been used in speed-sensitive cache due to its fast speed with low power
We propose a design of a high-density memory (HDM)
The simulation results indicated that the HDM has superior performance such as lower power consumption, high density (8 F2), higher speed, and enhanced anti-interference capability (~1 s), which indicate that the HDM may have potential application values in high-density SoC cache

Summary

Introduction

Static random-access memory (SRAM) has been used in speed-sensitive cache due to its fast speed with low power. A memory technology with comparable speed but higher density has been urged by the development of on-chip memory [1–3]. Studies have shown that devices based on this mechanism have the characteristics of fast speed and low power consumption, which makes it possible to study a semiconductor memory device based on the band–band tunneling mechanism. Compared with semiconductor memory based on the hot carrier injection mechanism and F-N tunneling mechanism, devices based on band-to-band tunneling have the advantages of low operation voltage and high speed [9–13]. In order to meet the requirements of fast-speed, high-density, and low-power memory, alternative architectures have been considered as promising candidates to replace the current product. The simulation results indicated that the HDM has superior performance such as lower power consumption, high density (8 F2), higher speed (operation speed less than 5 ns), and enhanced anti-interference capability (~1 s), which indicate that the HDM may have potential application values in high-density SoC cache

Device Structure and Main Process of HDM

Simulation Results and Discussion

Conclusions