A High-Density and Reconfigurable SRAM-Based Digital Compute-In-Memory Macro for Low-Power AI Chips

Abstract

This brief presents a high-density and configurable digital SRAM-based compute-in-memory (CIM) macro that performs multiply-and-accumulation (MAC) operations for low-power artificial intelligence (AI) applications. The proposed CIM macro has the following features: 1) the weight bit-serial activation bit-serial (WSAS) MAC arithmetic significantly reduces computing logic area overhead in digital CIM, leading to a much higher storage density; 2) This design supports fully configurable bit precision ranging from 1 to 16 bits of signed or unsigned weight and activation; 3) Weight and activation are both stored and computed within the CIM macro, which makes this design can be integrated into the system with less effort and has the potential to further reduce energy consumption from a system perspective. The layout has been implemented in 40-nm CMOS technology. Based on the post-layout simulation results, the design achieves a frequency of 625 MHz and energy efficiency of 497 TOPS/W at 1 bit and 1.94 TOPS/W at 16 bit.