A hierarchical switch matrix and interconnect resources test in Virtex-5 FPGA

Abstract

With increasing scale of Field Programmable Gate Arrays (FPGAs), architecture of interconnect resources (IRs) in FPGA is becoming more and more complicated. Switch matrix (SM) is one of the most important concepts in the IR architecture. Existing concept of the SM is no longer applicable to these high-end FPGAs. In this paper, based on analysis of the IR architecture in Virtex-5 FPGA, we come up with a concept of hierarchical SM. In the hierarchical SM, IRs are classified into several independent layers of wire segments with programmable-interconnect-point programmable switches (PIP-PSs) in between. The SM in Virtex-5 FPGA consists of several sub-SMs depending on types of wire segments, compared with only one SM in XC4000 FPGA. A full coverage test algorithm for IRs in Virtex-5 was studied by adopting hierarchical SM based repeatable building blocks and fault mapping method. An experiment in XC5LX110T using an in-house developed test system with boundary scan and bitstream readback was carried out. 56 configuration numbers are required to test the XC5LX110T in full coverage. The concept of hierarchical SM and test algorithm is also applicable to Virtex, Virtex-II, Virtex-4, Virtex-5, Virtex-6, 7-series and all Spartan series FPGA as long as SMs are used.