A hierarchical pattern representation format for proximity effect correction in E-beam lithography

Abstract

As the size of a circuit pattern is increased with the feature size reduced, the data size required to represent it grows rapidly. A critical issue in E-beam lithographic systems is the need to efficiently compact the pattern data and also reduce the proximity correction time. A hierarchical representation of circuit pattern, which utilizes the repetition in the layout geometry, is often employed in order to reduce the data size requirement. However, it has a negative implication in proximity effect correction, i.e. lengthening correction time. We have designed a compact data structure format which not only allows maintaining compactness of a hierarchical pattern representation, but also enables efficient searching the hierarchical representation, which is essential in minimizing correction time.