A hierarchical design of an application-specific instruction set processor for high-throughput FFT

Abstract

This paper presents a novel hierarchical design of an application-specific instruction set processor (ASIP) tailored for fast Fourier transformation (FFT), a kernel data transformation task in digital communication systems, to meet the stringent requirements on throughput and flexibility. We reconstruct the FFT computation flow into a scalable array structure based on an 8-point butterfly unit (BU). The array can easily expand along both the horizontal and vertical dimensions for any-point FFT computation, and contains the same structure for each horizontal stage. We incorporate custom register files to reduce memory access, and derive a regular data addressing rule accordingly. With the microarchitecture modifications, we extend the instruction set with three custom instructions. Our FFT ASIP implementation achieves a data throughput improvement of 866.5times, 5.9times, 2.3times over the standard FFT software implementation, one TI DSP processor, and one commercial ASIP - Xtensa's implementation, respectively. Meanwhile, the area and power consumption overhead of the custom hardware is acceptable.