Abstract
Due to the physical restriction of current CMOS technology, emerging technologies that have majority logic gate as a base component are being explored. The process of transforming from boolean network to the majority logic network is called majority logic synthesis. Hence, the contributions of this work is as follows: (i) a novel heuristic-driven tabular approach for majority logic synthesis has been presented that overcomes the scalability problem of previous synthesis algorithms, (ii) a heuristic named as matching difference (MD) is proposed to guide the synthesis process, (iii) a parameter named as cost of circuit (CoC) is proposed to maintain the trade-off between area and delay during majority logic synthesis, (iv) an extended library for majority logic synthesis based on 3-input and 5-input majority gates that help in delay reduction of majority circuit is presented, and (v) a post-synthesis optimization method is proposed based on majority algebra. Based on experiments with MCNC benchmarks, it is verified that the proposed approach accomplishes an average diminution of 24% at the majority level and 31% in the majority gate count. Further, while executing a case study with quantum dot cellular automata(QCA), the proposed methodology is able to achieve an average diminution of 36% in delay and 15% in circuit cost with a penalty of 2% in the area.
Highlights
T HE scaling of a transistor has major advantages, such as making transistors cheaper, faster, and energy-efficient, as described by Moore’s law [1]
In quantum dot cellular automata (QCA), a binary information is encoded within the electron pair configuration residing in a quantum cell, whereas in nano magnetic logic (NML), the magnetization stored in a single domain nanomagnets represents binary information that can be propagated by exploiting the magneto dynamic interaction among neighbor elements
This paper presented a novel heuristic-based cost-aware majority logic synthesis algorithm
Summary
T HE scaling of a transistor has major advantages, such as making transistors cheaper, faster, and energy-efficient, as described by Moore’s law [1]. Researchers proposed methods that can handle more than three variables presented in [20, 21, 22, 23], but these techniques utilized K-map for MLS. In [20], a disjoint concept was utilized for further improvement, whereas in [22] author proposed a methodology where each boolean function converts into a majority function twice: first, for original function; second, for its complement with the hope of developing a better majority circuit This increased the synthesis time by 2x. It is expected that a novel MLS methodology which does not use K-map so that approach can well utilize higher input majority gates. The major contributions of the paper areas follows: 1) A novel cost-aware heuristic-based tabular approach for majority/minority logic synthesis is proposed.
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