Abstract
By increasing the impact of process variation on the uncertainty of the delay of the gates, and also the need for increasing the number of test paths, delay test has become an essential part of the chip testing. In this paper, a heuristic test path selection method is proposed that is a combination of the non-optimal and optimal selection methods. In the first step of the proposed selection method, the search space is reduced by considering correlations between the paths. Next, by using ILP formulation, best paths from the reduced search space are selected. For the ILP formulation, we have proposed an objective function which considers correlation and the criticality of the paths. The results show that the delay failure capturing probability (DFCP) of the proposed path selection method for eight largest ITC'99 benchmarks, on average, is only about 3% smaller than the Monte Carlo method, while its runtime is about 1340 times smaller than the Monte Carlo approach.
Published Version
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