A heuristic fault based optimization approach to reduce test vectors count in VLSI testing

Abstract

In this work we have proposed a heuristic approach to reduce the test vector count during VLSI testing of standard ISCAS circuits. With the shrinking die-space and increasing circuitry on a single Integrated circuit, the number of test vectors required for testing is also increasing. The number of test vectors directly affects the total testing cost of a circuit. In this work fault based test vector optimization has been proposed. Here, test vectors have been reduced by extracting child test vectors and merging them. The proposed scheme helps in reducing the test vector count and has been tested successfully using single stuck at fault models. The results obtained illustrate the effectiveness of proposed scheme.