A HD 31fps $7\times 7$-View Light-Field Factorization Processor for Dual-Layer 3D Factored Display

Abstract

Factored displays [1]–[4] are a novel kind of computational display which provides a full-parallax glasses-free 3D viewing experience. Compared to other autostereoscopic techniques, factored displays provide greater depth of field, larger field of view, and smoother perspective switching without sacrificing image resolution. Figure 33.3.1 shows an example: a light field consisting of <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$7\times 7$</tex> -perspective multi views (MVs) is factorized into a set of dual-layer display views (DVs), and displaying the front and rear DVs on two corresponding LCDs can multiplicatively approximate the light field for 3D vision. A higher rank of factorization generates more frames for time-multiplexed display and can improve 3D fidelity with more computation. However, the light-field factorization demands massive memory bandwidth and large computation complexity and becomes a bottleneck for real-time factored displays. For instance, 126.8GB/s of DRAM bandwidth and 4.7TFLOPS of computation are required in a rank-4 factorization at 720p HD 30fps. It is expensive and energy-inefficient to realize these demands in general-propose processors. This paper presents a light-field factorization processor to address the design challenges of memory bandwidth and computational complexity through three key contributions: 1) a half-block-based factorization (HBBF) flow to decouple DRAM access from the iterative nature of factorization to save DRAM bandwidth; 2) a sparse-ray-sampling (SRS) method which reduces DRAM bandwidth and hardware complexity simultaneously; and 3) INT-hybrid optimization for the computation of light-field factorization to save chip area.