Abstract
Simulating human brain with hardware has been an attractive project for many years, since memory is one of the fundamental functions of our brains. Several memory models have been proposed up to now in order to unveil how the memory is organized in the brain. In this paper, we adopt spatio-temporal memory (STM) model, in which both associative memory and episodic memory are analyzed and emulated, as the reference of our hardware network architecture. Furthermore, some reasonable adaptations are carried out for the hardware implementation. We finally implement this memory model on FPGA, and additional experiments are performed to fine tune the parameters of our network deployed on FPGA.
Highlights
A spatio-temporal memory model has been proposed by Hu et al (2016)
The remaining part of this paper is organized as follows: in section 2, we introduce the adaptations of spatio-temporal memory (STM) model, to make it more suitable for hardware implementation
The recall layer has the same number of normal leaky integrate-andfire (LIF) neurons as layer I in order to respond to different inputs and transmit stimulus to layer II
Summary
A spatio-temporal memory model has been proposed by Hu et al (2016) Throughout the recall phase, hetero-associated memory is stored in the connections between input layer and layer I, which enables a timely response for a particular neuron assembly in layer I whenever a new pattern is introduced to input layer. The capability of pattern completion in this memory model is maintained by the lateral connections within neuron assemblies of layer I. A pattern is recalled if the neuron assembly related to that pattern fires spikes repetitively.
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