Abstract
This paper outlines the structure of the FIDIAS System, a high level synthesis tool being developed at the Departamento de Informática y Automática of the Universidad Complutense of Madrid. It also describes in a higher level of detail HARAL, the FIDIAS module charged with the hardware allocation subtask. A global branch and bound exploring algorithm is described, as well as some of the strategies used for bounding the accessible design space in order to reduce the time spent in the solution search. The goodness of these strategies is shown in detail, with the help of some examples.
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