Abstract
Dual edge triggered (DET) techniques are most liked choice for the researchers in the field of digital VLSI design because of its high-performance and low-power consumption standard. Dual edge triggered techniques give the similar throughput at half of the clock frequency as compared to the single edge triggered (SET) techniques. Dual edge triggered techniques can reduce the 50% power consumption and increase the total system power savings. The low-power glitch-free novel dual edge triggered flip-flop (DET-FF) design is proposed in this paper. Still now, existing DET-FF designs are constructed by using either C-element circuit or 1P-2N structure or 2P-1N structure, but the proposed novel design is designed by using the combination of C-element circuit and 2P-1N structure. In this design, if any glitch affects one of the structures, then it is nullified by the other structure. To control the input loading, the two circuits are merged to share the transistors connected to the input. In the proposed design, we have used an internal dual feedback structure. The proposed design reduces the delay and power consumption and increases the speed and efficiency of the system.
Highlights
Today, the flip-flops are widely used for data storage. e performance and fault tolerance ability of the devices are precisely affected by the flip-flops reliability, speed, and power consumption
Results and Analysis e proposed low-power glitch-free novel dual edge triggered ip- op design is performed through the SPICE simulator with Predictive Technology Model (PTM) 22 nm CMOS technology [15] with a power supply of 1 V. e channel lengths of all of the transistors are xed to 22 nm
We have presented a low-power glitch-free novel dual edge triggered ip- op which is designed with the mixed combination of 2P-1N and C-element structures. e glitch-free novel dual edge triggered flip-flop design is the novel and unique design because it is constructed by using two fault resistant structures
Summary
Dual edge triggered (DET) techniques are most liked choice for the researchers in the field of digital VLSI design because of its highperformance and low-power consumption standard. Dual edge triggered techniques can reduce the 50% power consumption and increase the total system power savings. E low-power glitch-free novel dual edge triggered flip-flop (DET-FF) design is proposed in this paper. Still existing DET-FF designs are constructed by using either C-element circuit or 1P-2N structure or 2P-1N structure, but the proposed novel design is designed by using the combination of C-element circuit and 2P-1N structure. In this design, if any glitch affects one of the structures, it is nullified by the other structure. We have used an internal dual feedback structure. e proposed design reduces the delay and power consumption and increases the speed and efficiency of the system
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