Abstract
A dual edge triggered (DET) flip-flop responds to both edges of the clock. Hence the usage of DET flip-flops reduces clock related power dissipation in digital VLSIs. DET flip-flops are also desirable in high performance applications since the clock frequency can be halved for the same data throughput. We compare several published implementations of DET flip-flops for performance, power consumption. A modified DET flip-flop is proposed that exhibits improved specifications. Preliminary simulations are also carried out to evaluate DET flip-flop sensitivities to VDD, temperature, clock and data rise times, etc.
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