A gate driver circuit design for SiC MOSFET based three level NPC inverter with reduced high frequency switching noise

Abstract

Superior characteristics of silicon carbide (SiC) MOSFETs such as higher breakdown voltage, higher band-gap energy, lower switching losses, lower on-state resistance turns out to be the best alternative to silicon (Si) MOSFETs and Si-IGBTs for high power density converters. However, its low threshold voltage and lower transconductance value increases difficulties in the driver circuit design due to high frequency noise and EMI problems. Therefore, appropriate selection of driver circuit parameters is necessary to avoid high frequency switching losses, noise and EMI effect which further affects the performance of power converters and decreases its efficiency. In this paper, a simple gate driver circuit design for SiC MOSFET based three level diode clamped inverter is presented. Step by step selection procedure of driver circuit components is explained. A 10kVA, three phase, three level inverter is developed and performance of proposed driver circuit in eliminating high frequency noise, rise in the gate-source voltage spikes and electromagnetic interference (EMI) effect is experimentally evaluated.