A GaAs MESFET macrocell array

Abstract

An ultra-high-speed GaAs macrocell array is described which uses a three-level series-gate low-power source-coupled FET logic (LSCFL) as a basic circuit and a 0.4- mu m-gate flat-gate self-aligned implantation for n/sup +/-layer technology-2 (FG-SAINT-2) as a fabrication technology. The chip consists of 50 macrocells and is the equivalent of 250 gates. A typical propagation delay of unloaded ring oscillators and a typical toggle frequency of 1/4 frequency dividers fabricated on the macrocell array are 30 ps and 7.5 GHz, respectively. The basic cell is composed of three-level series gate LSCFL using all-differential signals; this circuit has twice the speed of a single-ended SCFL because it involves only one-half logic swing with the same noise margin. To verify the LSI performance, a 2*2 asynchronous transfer mode (ATM) switch element (150 equivalent gates) was fabricated on the macrocell array. The measured waveforms of the switch at 2 Gb/s are shown. The equivalent critical path gate number of the chip is 10 between flip-flops; therefore an average gate delay time of 50 ps is obtained. >