A functional verification environment

Abstract

The lack of flexible verification environments that allow verification components reuse across ASIC design projects keep the verification cost very high. Design engineers have made design reuse central in bringing the design effort's complexity back to a manageable size. To reduce development time and effort, significant design blocks are reused from one project to the next. Considering the fact that verification consumes more resources than design does in a typical design project, it would be of great value to build verification components that are modular and reusable. In this paper, we present a verification methodology that utilizes a bottom-up, functional design verification strategy that encourages building and using modular and reusable verification components. At the core of this approach is a library of components specially designed for re-use. This verification approach is presented in the context of the relatively new IEEE ten Gigabit Ethernet standard (IEEE 802.3ae).