A Fully Integrated SAR ADC Using Digital Correction Technique for Triple-Mode Mobile Transceiver

Abstract

This paper presents a fully integrated SAR ADC for GSM/WCDMA/LTE triple-mode transceiver (RFIC) with non-binary DAC structure and digital correction techniques. All blocks including input buffer, ADC core, bias, references and ADC logics are implemented in a single chip with a small die area of 0.044 mm $^{2}$ /0.066 mm $^{2}$ for ADC core and ADC logic. The proposed ADC does not require off-chip decoupling capacitor for reference voltage by employing charge-sharing topology. Reconfigurable structure is used for multi-mode operation by adjusting ADC speed and noise, where SNDR of 67.0 dB in GSM and 58.2 dB in WCDMA/LTE are achieved at the sampling frequencies of 52 MS/s and 80 MS/s, respectively.