A Fully Integrated HF-Band Passive RFID Tag IC Using 0.18-$\mu\hbox{m}$ CMOS Technology for Low-Cost Security Applications

Abstract

We present a fully integrated small-size HF-band passive RF identification (RFID) tag chip with authentication and security functions. The design of the RF transceiver and digital control of the tag IC is based on the International Organization for Standardization-14443 type-B protocol. The design of the key analog part of the tag IC is presented, which includes a robust demodulator for 10% amplitude shift keying envelope detection, a high-quality random number generator, and a voltage regulator that can handle a range of output load currents. To implement the secure data transaction with a reader, a 128-b advanced encryption standard (AES) with a new cyclic key generation is used for the data encryption and decryption. An on-chip 4-kb electrically erasable programmable ROM (EEPROM) is used to support the AES operation, tag identification, and tag self-destruction. The read and write accesses of the EEPROM are performed using a 128-b wide buffer with self-timed bursts. The tag chip is fabricated in a one-poly six-metal low-power 0.18-μm CMOS process with a CoSi <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> Schottky diode and EEPROM process. Using the scaled-down CMOS technology, the size of the tag chip is only 1.1 × 1 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , providing a cost-effective solution for everyday RFID applications.