Abstract

This article presents a fully integrated 40-Gb/s phase locked clock and data recovery (CDR) circuit with 1:4 demultiplexer (DEMUX) in International Business Machines (IBM) 90-nm CMOS technology.The CDR circuit incorporates a novel eight-phase CL ladder filtering voltage-controlled oscillator and a quarter rate bang-bang phase detector. The 40-Gb/s input data are sampled with eight parallel differential master-salve flip-flops every 12.5 ps and the 40-Gb/s data are demultiplexed into four 10-Gb/s outputs when the CDR circuit is phase locked. The recovered and frequency divided 10-GHz clock has a phase noise of −101.01 dBc/Hz at 1 MHz offset and a peak to peak jitter of 3.4 ps. The CDR and 1:4 DEMUX consumes 72 mW from a 1.2 V supply excluding out buffers. © 2012 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:170–173, 2013; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27248

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call

Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.