Abstract
All cryptography systems have a True Random Number Generator (TRNG). In the process of validating, these systems are necessary for prototyping in Field Programmable Gate Array (FPGA). However, TRNG uses an entropy source based on non-deterministic effects challenging to replicate in FPGA. This work shows the problems and solutions to implement an entropy source based on frequency collapse in multimodal Ring Oscillators (RO). The entropy source implemented in FPGA pass all SP800-90B tests from the National Institute of Standards and Technology (NIST) with a good entropy compared to related works. The TRNG passes all NIST SP800-22 with and without the post-processing stage. Besides, the TRNG and the post-processing stage pass all tests of Application notes and Interpretation of the Scheme (AIS31). The TRNG implementation on a Xilinx Artix-7 XC7A100TCSG324 FPGA occupies less than 1% of the resources. This work presents 0.62 μs up to 9.92 μs of sampling latency and 1.1 Mbps up to 9.1 Mbps of bit rate throughput.
Highlights
Random Number Generators (RNG) conform a crucial part of cryptographic systems
To reduce the systematic mismatch, we configure the placement, routing, and Look-Up Tables (LUTs) constraints according to the entropy source model. We reduce this according to the analytical model of three multimodal Ring Oscillators (RO) proposed by Yang et al [8], and including the systematic mismatch introduced by the Field Programmable Gate Array (FPGA) implementation
The True Random Number Generator (TRNG) is based on the frequency collapse phenomenon using a multimodal RO and a regular RO
Summary
Random Number Generators (RNG) conform a crucial part of cryptographic systems. RNG circuits are implemented as in-core key generation, where the data can be ciphered with such random keys. Ronaldo Serrano et al.: A Fully Digital True Random Number Generator with Entropy Source Based in Frequency Collapse. We implement the entropy source based on frequency collapse in multimodal RO. The odd edges analytical model stated in (2) determines that the frequency collapse depends only on the systematic mismatch and random jitter. When the jitter accumulation achieves the limit by two pulses crash, the small pulse is lost, indicating the frequency collapse At this moment, the PFD indicates the REF frequency is higher compared to the RNG frequency, and the logic of the capture stage triggers the valid signal
Sign-in/Register to view highlights & summary Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
