A Fully Characterizable Asynchronous Multiphase Delay Generator

Abstract

A fully characterizable, 128-stage asynchronous Multiphase Delay Generator (MDG) integrated in standard 0.35 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\mu{\hbox {m}}$</tex></formula> CMOS technology is presented. The circuit consists of a mirror Voltage-Controlled Delay Line (VCDL), driven by a Delay-Locked Loop (DLL), and an analog memory block. The master DLL ensures the stability over temperature and the absolute precision of the delay, whereas the mirror VCDL allows an asynchronous operation of the MDG with respect to the DLL reference clock. The memory block carries out a precise stage-to-stage delay and jitter characterization by analog sampling the state of the mirror VCDL upon an external request. Two versions of the circuit differing by their VCDL layout configurations were processed in order to compare their absolute time accuracy and jitter performance. In the first variant the two delay lines were laid out in an interlaced arrangement, whereas in the second, the mirror VCDL was positioned under the master VCDL. A maximal temporal dynamic range of 125 ps–1 ns was achieved. The single-stage delay variation with temperature was less than 1% over the 10–60 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$^{\circ}{\hbox {C}}$</tex></formula> range considered. The mean RMS jitter level per stage remained below 3% of the elementary delay over the entire dynamic range of the MDG for both circuit versions.