Abstract
Image feature detection is a key task in computer vision. Scale Invariant Feature Transform (SIFT) is a prevalent and well known algorithm for robust feature detection. However, it is computationally demanding and software implementations are not applicable for real-time performance. In this paper, a versatile and pipelined hardware implementation is proposed, that is capable of computing keypoints and rotation invariant descriptors on-chip. All computations are performed in single precision floating-point format which makes it possible to implement the original algorithm with little alteration. Various rotation resolutions and filter kernel sizes are supported for images of any resolution up to ultra-high definition. For full high definition images, 84 fps can be processed. Ultra high definition images can be processed at 21 fps.
Highlights
Image matching is a typical problem in computer vision
In order to compute general purpose Scale Invariant Feature Transform (SIFT) features on an field-programmable gate array (FPGA) that are suitable for multi-view 3D reconstruction, the rotation of the images must be taken into account [5], [6]
With PoIs occurring at most on every other pixel and the requirement of the whole window to be within the image, this does not lead to a degradation of the throughput if a FIFO is used to buffer some potential clusters of descriptors
Summary
Image matching is a typical problem in computer vision It is applied, amongst other things, in the fields of object recognition, motion tracking and to generate 3D objects from multiple images. All of the implementations neglected parts of the algorithm which were irrelevant for their particular use case such as robotic vision for a mooving vehicle, where the rotation of the SIFT descriptor can be neglected [4]. This results in a degeneration of the accuracy and versatility of the generated descriptors.
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