A novel SIFT architecture and ASIC implementation for real time SOC application

Abstract

Local feature detection and description algorithms such as scale invariant feature transform (SIFT) algorithm are among the most commonly used techniques in computer vision. They are used mainly to detect and extract high-level information from low-level (pixel) information in images. These algorithms are computationally intensive and its pure software implementations are far from reaching real-time performance especially on embedded systems with limited computational power. In this paper, an Application-Specific Integrated Circuit (ASIC) implementation of the SIFT algorithm is proposed that is suitable for real-time image processing. In the Gaussian scale space generation step, several techniques were used to substantially reduce the hardware complexity: the multiplierless multiple constant multiplication, the symmetrical property of Gaussian mask in addition to the common sub expression elimination algorithm. Through the re-arrangement of SIFT’s 128 values in a specific approach, a new multi-ported memory is implemented to reduce the memory size. Furthermore, a novel mechanism is applied to continuously monitor the active window in the input and the intermediate results. The proposed technique does not only improve the performance of the SIFT implementation, but it also keeps the features extraction accuracy exactly the same as the software implementation. In this work, for an image size of $$256 \times 256$$ a frame rate of 56 fps was achieved. Additionally, the results confirm that the proposed architecture has lower hardware and memory costs compared to other works in the literature (FPGA based implementations). Lastly this architecture was implemented using Standard Cell Library Based ASIC flow using 65 nm low power GF library, it occupied an area of 1.4 $${{{\mathrm{mm}}}^2}$$ and consumed a total power of 30.4604 mW which makes it very suitable for integrated System on Chips (SoC) applications.