A full-transistor fine-grain multilevel delay element with compact regularity layout

Abstract

This paper proposes a full-transistor multilevel delay element (DE) implemented by 65 nm/1.8 V CMOS technology. 10 mV/LSB and 50 mV/LSB control voltages are employed to realize the fine-grain and coarse tuning for multilevel delay adjustment while maintain the duty cycle of input pulse. In physical design, a novel transistor array with a compact regularity layout is adopted to mitigate process variation. According to the post-layout simulation analysis, compared with two traditional delay elements, the proposed DE has particular advantages in terms of the layout area as well as achieves the acceptable merely 2× power consumption and 22.9% delay quantization error in linearity accuracy. The effective 2 MHz bandwidth and nano-second delay range is applicable to a low/medium frequency clock compensation system.