A low-power rail-to-rail input-range linear delay element circuit

Abstract

Delay elements are one of the key components in many time-domain circuits such as time-based analog-to-digital converters. In this paper, a new rail-to-rail current-starved delay element is proposed which not only presents good linearity for the voltage-delay curve over the input range of ground to supply voltage, but also it consumes a dynamic power only during the transition times without consuming any static power. The proposed delay element is designed and simulated in a 0.13-µm CMOS technology with a supply voltage of 1.2V. Post-layout simulation results demonstrate that the proposed circuit has a linear voltage-delay transfer function with a voltage-to-time gain of −1.33ps/mV. Moreover, when samples of a full-scale sin-wave input signal are applied to the proposed circuit with a clock frequency of 100MHz, the power consumption is 30µW, and signal-to-noise-and-distortion ratio (SNDR) of the output delay times is 30.4dB, making it suitable for use in a time-based analog-to-digital converter with up to 5-bit resolution.