A Full Adder Based on Hybrid Single-Electron Transistors and MOSFETs at Room Temperature

Xiaobao Chen,Zuocheng Xing,Bingcai Sui

doi:10.1007/978-3-642-41635-4_26

A Full Adder Based on Hybrid Single-Electron Transistors and MOSFETs at Room Temperature

Xiaobao Chen, Zuocheng Xing + Show 1 more

https://doi.org/10.1007/978-3-642-41635-4_26

Copy DOI

Publication Date: Jan 1, 2013

Citations: 16

Affiliation: National University of Defense Technology, Institute of Microelectronics

#Hybrid Single-Electron Transistors #Single-electron Transistors + Show 8 more

Abstract
Full-Text
Similar Papers

Abstract

A full adder based on hybrid single-electron transistors (SET) and MOSFETs (SETMOS) at room temperature is proposed in this paper. Because the SET can play the same role as compensatory MOSFETs, we design a fuller adder with hybrid SETMOS. Further more, we simulate the logic element by HSPIC and the simulation result shows that the logic element implements the function of a full adder. To compare our work with conventional CMOS logics, which significantly reduces area and power consumption.

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call

Similar Papers

Paper Title

Journal

Date

Author

View more papers

Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.