A framework to analyze processor architectures for next-generation on-board space computing

Abstract

Due to harsh and inaccessible operating environments, space computing presents many unique challenges with respect to stringent power, reliability, and programmability constraints that limit on-board processing performance and mission capabilities. However, the increasing need for real-time sensor and autonomous processing, coupled with limited communication bandwidth with ground stations, are increasing the demand for high-performance, on-board computing for next-generation space missions. Since currently available radiation-hardened space processors cannot satisfy this growing demand, research into various processor architectures is required to ensure that potential new space processors are based on architectures that will best meet the computing needs of space missions. To enable this research, we present a novel framework to analyze potential processor architectures for space computing. By using this framework to analyze a wide range of existing radiation-hardened and emerging commercial processors, tradeoffs between potential space computing architectures can be determined and considered when designing new space processors or when selecting commercial architectures for radiation hardening and use in space missions. We demonstrate the ability of the framework to generate data for various architectures in terms of performance and power, and analyze this data for initial insights into the effects of processor architectures on space mission capabilities. The framework provides a foundation for the analysis of a broad and diverse set of processor architectures for potential use in next-generation, on-board space computing.