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Abstract
The TTM/RTTL (timed transition model with real-time temporal logic) framework is presented for modeling, specifying, and analyzing real-time discrete-event systems. TTMs are used to represent the process of the plant and its controller. RTTL is the assertion language for specifying plant behavior and verifying that a controller satisfies the specification. The framework adapts features from the program verification literature which are useful for posing problems of interest to the control engineer, such as modular synthesis and design. Examples are used to illustrate the ideas presented. The authors' published analytical results are summarized and referenced. >
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