A Four-Phase Passive Mixer-First Receiver With a Low-Power Complementary Common-Gate TIA

Indrajit Das,Nagarjuna Nallam

doi:10.1109/access.2020.3041687

Abstract

This paper presents a four-phase passive mixer-first receiver using a common-gate (CG) trans-impedance amplifier (TIA), instead of a conventional shunt-feedback amplifier. The four-transistor TIA used in this work combines current-reuse with cross-coupled $g_{m}$ -boosting to achieve a reduced noise figure (NF) at low power levels. Moreover, complementary derivative-superposition (CDS) linearization within the TIA helps to improve the linearity with no additional power overhead. A prototype receiver is implemented in a 180 nm CMOS technology. The receiver operates from 0.3 to 1.3 GHz with a conversion gain of 21.9 dB. In measurements, the receiver achieved a noise figure of 5.8 dB and an in-band (IB) IIP3 of +7.2 dBm while consuming 0.34 mW power per TIA at 1 GHz. The measured spurious-free dynamic range (SFDR) at 1 GHz is 76.9 dB.

Highlights

S EVERAL new wireless communication standards are being proposed to satisfy the ever-increasing user requirements
The dynamic power consumption is due to the clock buffers driving the mixer switches, while the static power consumption is due to the radio frequency (RF) low noise amplifier (LNA) [8]–[11] and the baseband (BB) trans-impedance amplifier (TIA)
Typical trade-offs involved in the design of the TIA for a mixer-first receiver are shown in Fig. 1(b) [40]

Summary

INTRODUCTION

S EVERAL new wireless communication standards are being proposed to satisfy the ever-increasing user requirements. Various techniques are proposed in [13]–[15], [34]–[36] to reduce the power consumption in passive mixer-first receivers. The objective of the current work is to investigate a TIA topology that is suitable for a high-linearity and low power mixer-first receiver. PROPOSED RECEIVER ARCHITECTURE Fig. 2 shows the block diagram of the implemented fourphase mixer-first receiver using the CCC-CCG TIA in the baseband. The intrinsic third-order nonlinearity of the TIA can be reduced by biasing the pMOS and nMOS transistors near the zero-crossings of gmp and gmn, respectively.

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LINEARITY

CONCLUSION