A four quadrant high-speed CMOS analog multiplier based on the flipped voltage follower cell

Abstract

In this work the design and implementation of a High-Speed Four-Quadrant CMOS Analog multiplier is presented. The proposed multiplier uses the Gilbert cell as the main core. However, instead of processing both input and output signals in voltage or current mode, the “x” input signal is applied in voltage mode while the “y” input signal and “o” output signal are processed in current-mode. This approach is achieved by means of using very-low-impedance nodes at the “y” and “o” ports which also helps to enhance the overall bandwidth of the proposed multiplier. Both very-low-impedance nodes are implemented using the Flipped Voltage Follower (FVF) as high-speed high-performance low-voltage current mirror. The implemented circuit shows a bandwidth of 260 MHz for a 50Ω‖30pF load, presents a 1.5% THD at 100 MHz, and consumes 7.5 mV using a ±1 V symmetric power supply. In order to validate theory and simulations, a prototype of the multiplier was fabricated and tested using a 0.5 μm CMOS standard fabrication process; a silicon area consumption of 520 μm × 70 μm was observed. Measurements shows that the proposed multiplier is suitable for its implementation in the low corner of the Very High Frequency (VHF) band.