Abstract
Flipped voltage follower (FVF) cell is used for designing low-voltage/low-power analog circuits. It can operate with a single supply voltage, less than the sum of the threshold voltages of a PMOS and NMOS transistor. The three different configurations of the FVF cell namely conventional FVF, FVF using level shifter (FVFLS) and FVF using bulk driven technique (FVFBD) are presented. Various parameters such as input/output swing, gain, bandwidth and power dissipation of all the configurations are reported. It is observed that FVFLS and FVFBD have improved input/output swing. Also, maximum gain can be achieved using FVFLS whereas maximum bandwidth can be obtained using FVFBD. The circuits have been simulated using Cadence Design tool in 0.18 µm CMOS technology.
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